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    政大機構典藏 > 資訊學院 > 資訊科學系 > 會議論文 >  Item 140.119/84121


    Please use this identifier to cite or link to this item: https://nccur.lib.nccu.edu.tw/handle/140.119/84121


    Title: Verification Process for Digital IC Design
    Authors: Jang, Hung-Chin;Lien, Yao-Nan;Chou, Shi-Kung
    張宏慶;連耀南;周世剛
    Contributors: 資科系
    Keywords: 驗證模型、IC 設計
    Date: 2011-07
    Issue Date: 2016-04-11 16:05:00 (UTC+8)
    Abstract: 本研究旨在為IC 設計之驗證，設計一套有助於提高IC 產品品質的軟體工程驗證模型 。過去在IC設計領域並沒有一套完整流程，明確規範每個驗證步驟該有的程序與方法。我們參考軟體開發模型中的現有架構並加以修改，設計出一套符合軟體工程需求的標準流程(SOP)，藉由該流程，IC 驗證能被標準化，並能明確掌握所需時程與人力，降低成本，提高產能。由於一個軟體設計流程需要歷經多年的使用改進方能達到成熟階段。本研究所發展的驗證流程與工具不僅能適用於USB3.0 開發，並能適用於任何一種數位IC 的驗證流程。
    Relation: 2011 Joint Conference on Taiwan Software Engineering (TCSE), Taipei, Taiwan, Jul 8-9, 2011
    Data Type: conference
    Appears in Collections:[資訊科學系] 會議論文

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