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政大機構典藏 > 政大學報 > 第50期 > 期刊論文 > Item 140.119/102422

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Title:	An Approach to the Increase of the Performance of VLSI System by Implementing Systolic Array
Authors:	楊立人 Yang, Li-jen
Contributors:	應用數學系
Date:	1984-12
Issue Date:	2016-09-30 11:42:56 (UTC+8)
Abstract:	本文主要是研究有關電腦中微處理機內部資料傳送之另一簡捷方法。當初美國卡內基－－梅隆大學(Carnegic-Mellon University)電腦系孔教授(Prof. H. T. KUNG)之所以取收縮陣列來做此種傳送方法之名是因為此種處理方法有如人體心臟之跳動，十分有節奏一放一縮的運作著。有關收縮陣列方面之論著已不在少數，但直至目前為止，彼等之解決方法大致只能將(n+1)x(n+1)之線性方程式系統所用之傳輸時間減至Bareiss所提出之Order(n2)或Bitmead & Anderson所提出的Order (nlog2n)。如果n值不大，Order(nlog2n)所花的時間會較長，換句話說，即其速度反而會比Order(n2)要來得慢，同時其解法也比較繁複。據本文以Bareiss所提出之解法做修正並推衍之結果，吾人理論上似可利用一維之收縮陣列將超大型電腦之線性方程式系統使用之時間與記憶空間具減為Order(n)。A systolic system is a network of processors which rhythmically compute and pass data through the system. Many basic matrix computations can be pipelined efficiently on systolic networks having an array structure. In this paper we are trying to find a better solution for an (n+1) x (n+1) system of linear equations by using a one-dimensional systolic array. In the algorithms implemented shown that it requires only order(n) time and order(n) storage.
Relation:	國立政治大學學報, 50, 59-76
Data Type:	article
Appears in Collections:	[第50期] 期刊論文

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